This application relates to copending U.S. patent application Ser. No. 08/013,319, filed Feb. 5, 1993, which is hereby incorporated herein by reference.
This invention is directed, in general, to microstructures and to a process for fabricating them and more particularly, to microelectromechanical and microoptomechanical structures and to a thermal oxidation process for fabricating complete structures including released, movable elements and connectors such as pads, runners, electrodes, and the like on a substrate, and for electrically isolating such structures.
Recent developments in micromechanics have successfully led to the fabrication of microactuators utilizing processes which have involved either bulk or surface micromachining. The most popular surface micromachining process has used polysilicon as the structural layer in which the mechanical structures are formed. In a typical polysilicon process, a sacrificial layer is deposited on a silicon substrate prior to the deposition of the polysilicon layer. The mechanical structures are defined in the polysilicon, and then the sacrificial layer is etched partially or completely down to the silicon substrate to free the structures.
The initial research into surface micromachining established the viability of the technology. Moving rotors, gears, accelerometers, and other structures have been fashioned through the use of such a process to permit relative motion between the structures and the substrate. This process relies on chemical vapor deposition (CVD) to form the alternating layers of oxide and polysilicon and provides significant freedom in device design; however, CVD silicon is usually limited to layers no thicker than 1-2 .mu.m, since residual stress in thicker layers overwhelms the structure and causes curling. Thus, although a large variety of layers can be combined to form very complicated structures, each layer is limited in thickness. In addition, the wet chemistry needed to remove the interleaved oxide layers often takes tens of hours of etching to remove, and once released the structures often reattach or stick to the substrate because of static electricity, and this requires elaborate process steps to overcome. The structures made of polysilicon inherently have a crystalline structure which has low breaking strength because of grain sizes, as well as electronic properties which are inferior to single crystal silicon. Furthermore although this technology is well established, it is not easily scaled for the formation of submicron, high aspect ratio mechanical structures.
In bulk micromachining, a silicon substrate is etched and sculpted to leave a structure. This has typically been done using wet chemical etchants such as EDP, KOH, and hydrozine to undercut single crystal silicon structures from a silicon wafer. However, such processes are dependent on the crystal orientation within the silicon substrate, since the chemistry etches as much as ten times faster in some crystallographic planes of silicon than in other planes. Although the shapes can be controlled to some degree by the use of photolithography and by heavy implantation of boron, which acts as an etch stop, it is difficult to control the process and accordingly, the type, shape and size of the structures that can be fabricated with the wet chemical etch techniques are severely limited. In particular, wet etch processes are not applicable to small (in the range of one micron or less) structure definition, because they are not controllable on that scale.
A dry bulk micromachining process which utilizes thermolateral oxidation to completely isolate 0.5 .mu.m wide islands of single crystal silicon is described, for example, in the article entitled "Formation of Submicron Silicon-On-Insulator Structures by Lateral Oxidation of Substrate-Silicon Islands", Journal of Vacuum Science Technology, B 6(1), Jan./Feb. 1988, pp. 341-344, by S. C. Arney et al. This work led to the development of a reactive ion etching (RIE) process for the fabrication of submicron, single crystal silicon, movable mechanical structures wherein the oxidation-isolation step described in the Arney et al publication was replaced with an SF.sub.6 isotropic release etch. This process, which allowed the release of wider structures, in the range of 1.0 .mu.m, and deeper structures, in the range of 2-4 .mu.m, is described in U.S. patent application Ser. No. 07/821,944, filed Jan. 16, 1992, now U.S. Pat. No. 5,198,390, assigned to the assignee of the present application. As there described, this dry etch process utilizes multiple masks to define structural elements and metal contacts and permitted definition of small, complex structures in single crystal silicon, and was easy to implement. However, the second lithography step was difficult to apply to deeper structures, particularly because of problems in aligning the second mask. Furthermore, that process relied upon the formation of a silicon dioxide layer on a single crystal silicon substrate, but since other materials such as GaAs or SiGe do not generate an oxide layer the way silicon does, the process could not be transferred to such other substrate materials.
In copending U.S. patent application Ser. No. 07/829,348, filed Feb. 3, 1992, now abandoned in favor of U.S. Ser. No. 08/171,965, filed Dec. 22, 1993, and assigned to the assignee of the present application, a process for releasing micromechanical structures in single crystal materials other than silicon is described. This process uses chemically assisted ion beam etching (CAIBE) and/or reactive ion beam etching (RIBE) to make vertical structures on a substrate, and uses reactive ion etching (RIE) to laterally undercut and release the structure. The process utilizes multiple masks, however, and thus encountered similar problems to the silicon process described above in the formation of deeper structures, and in the alignment of the second mask.
The use of single-crystal materials for mechanical structures can be beneficial, since these materials have fewer defects, no grain boundaries and therefore scale to submicron dimensions while retaining their structural and mechanical properties. In addition, the use of single-crystal materials, particularly single crystal silicon and gallium arsenide, to produce mechanical sensors and actuators can facilitate and optimize electronic and photonic system integration. For example, single crystal silicon structures having a very small mass can resonate without failure at 5 MHz for 2 billion cycles with a vibrational amplitude of plus or minus 200 nm. Accordingly, the fabrication of submicron mechanical structures with high aspect ratios would be highly desirable.
In copending application Ser. No. 08/013,319 a single-mask, low temperature (less than about 300.degree.), self-aligned process for the fabrication of microelectromechanical (MEM) structures is described, the process allowing the fabrication of discrete MEM devices as well as the integration of such structures on completed integrated circuit wafers. The process, known as Single Crystal Reactive Etching And Metallization ("SCREAM I"), may be used to produce a variety of sensor devices such as accelerometers, as well as a variety of actuator devices, resonators, movable optical reflectors, and the like, either as separate, discrete devices on a substrate, or as components on previously-fabricated integrated circuits.
The SCREAM-I process is a dry bulk micromachining process which uses reactive ion etching to both define and release structures of arbitrary shape, and to provide defined metal surfaces on the released structure as well as on stationary interconnects, pads and the like. The earlier process defined in the above-mentioned copending application Ser. No. 07/821,944 also permitted fabrication of microstructures, but required two masks to define the structural elements and the metal contacts. The invention of Ser. No. 08/013,319 was developed from that earlier process, but improved on it by extending the structural depth to about 10 to 20 .mu.m, permitting formation of beam elements 0.5 .mu.m to 5 .mu.m in width, eliminating the second mask/lithography step of the prior process, and allowing all structural elements, including movable elements such as beams and stationary elements such as interconnects, beams and contact pads, to be defined with a single mask so that the metal contacts applied to the structure are self-aligned.
The process relied, in general, on the formation of a dielectric mask on a single-crystal substrate such as silicon, gallium arsenide, silicon germanium, indium phosphide, compound and complex structures such as aluminum-gallium arsenide-gallium arsenide and other quantum well or multilayer super lattice semiconductor structures in which movable released structural elements electrically isolated from surrounding substrate materials and metallized for selective electrical connections could be fabricated using a single mask. The structure so fabricated could be discrete; i.e., fabricated in its own wafer, in which case any of the aforementioned substrate materials could be used, or it could be integrated in a silicon integrated circuit wafer, in which case the substrate material would be silicon, allowing low temperature processing in accordance with the invention.
Complex shapes can be fabricated in accordance with the invention described in Ser. No. 08/013,319, including triangular and rectangular structures, as well as curved structures such as circles, ellipses and parabolas for use in the fabrication of fixed and variable inductors, transformers, capacitors, switches, and the like. Released structures were fabricated for motion along X and Y axes in the plane of the substrate, along a Z axis perpendicular to the plane of the substrate, and for torsional motion out of the plane of the substrate.
In essence, the invention permitted fabrication of released structures and the subsequent metallization of such structures with a single dielectric mask by using theft mask to define deep isolating trenches completely around the structures, undercutting these structures to selectively release them and to produce cavities at the bases of surrounding mesas, and then metallizing the exposed surfaces. The undercutting and cavity formation broke the continuity of the deposited metal, thereby electrically isolating the metal on released structures and defined mesas from the metal on the bottom of the trenches, and a dielectric layer isolated the metal from the underlying substrate. The elements defined by the trenches were interconnected by the metal layer so that released structures could be electrically connected through the metal layer to pads in the surrounding mesas, with interconnects provided in selected locations and with the interconnects and pads also being defined by the trenches.
When the foregoing single mask process is carried out on a substrate or wafer integrally with existing circuitry, the low temperature process is preferred to prevent damage to the existing circuitry. The process of the copending application Ser. No. 08/013,319 forms deep, narrow trenches to define the isolated and released structures and thereby to produce high aspect ratio structures which can be metallized on their side walls for high capacitance between adjacent walls. In addition, the process permits a deep etching below the released structures to reduce parasitic capacitance between the released structures and metal on the trench floor. The etching process also produces extended cavities in the side walls of the mesas surrounding the released structures so as to reduce leakage current between metal on the side walls and on the trench floor. The metallization on the released structures cooperates with metallization on mesa side walls and metallization on the trench floors to capacitively control and/or sense horizontal and vertical motion of the released structure.
If desired, it is also possible to carry out additional steps after completion of the single mask processing described above to modify the resulting structure. For example, an additional masking step can permit variation of the spring constant of a released beam. In addition, a membrane can be added to released structures to increase their weight for use in accelerometers, and these membranes can be polished for use as movable mirrors. Additional steps may be used to connect metal layers to external circuitry, as by way of vias, and plural layers can be fabricated to form superimposed structures.
A wide range of devices can be fabricated utilizing the process of the invention described in Ser. No. 08/013,319. As noted above, the process is independent of crystal structure in the substrate, so that essentially any shape can be fabricated and released. Thus, single or multiple fingers cantilevered to a side wall of a substrate and extending outwardly over a trench bottom wall, and various grids and arrays can be fabricated and various electrical components can be formed. These various structures may be referred to as "beams" or "released beams", it being understood that such beams or released beams can be of any desired shape and can be single or multiple structures.
The metallization of selected walls and surfaces of the beams and surrounding substrate allows capacitive control and sensing of horizontal motion in the released structures, while metallization of the trench bottom wall allows control and sensing of vertical motion. By providing a relatively wide released structure, for example in the form of a grid or plate,, supported axially by single beams to a surrounding mesa wall, and by selectively applying a potential between one side or the other of the plate and the metal on the trench bottom, selective torsional rotation of the plate about the axis of its supporting arms can be produced. Such a torsional rotation of a plate has numerous applications; for example, in optics.
The released structures can be in the form of, for example, a single beam which serves as an accelerometer or a sensor and which is movable horizontally and vertically or in the form of plural beams in side by side parallel arrangement, or in various other arrays. Plural beam structures can work together, for example moving horizontally toward and away from each other to form "tweezers", or can have varying characteristics, such as thickness, to provide varying responses and thus to provide a wide range of motion or sensitivity in, for example, an accelerometer. Furthermore, various grid-like arrays may be provided to add mass or to provide torsional motion as described above.
The basic single mask process described in Ser. No. 08/013,319 can be outlined as follows.
First, a dielectric layer of oxide or nitride is deposited on a wafer or substrate, this layer serving as the single mask throughout the remainder of the steps. A standard PECVD process is used because of its high deposition rate and low deposition temperature. Thereafter, resist is spun, exposed and developed on the mask layer. Standard photolithographic resist techniques are used to define the desired beams, pads, interconnects and like structures. Thereafter, the pattern produced in the resist is transferred from the resist to the mask dielectric using, for example, CHF.sub.3 magnetron ion etching (MIE) or RIE.
An O.sub.2 plasma etch may be used to strip the resist layer, and the patterned dielectric mask is then used to transfer the pattern into the underlying wafer to form trenches around the desired structures. A deep vertical reactive ion etch (RIE) or chemically assisted ion beam etch (CAIBE) is required for this purpose. Depending on the choice of structure height, the trenches may be from 4 to 20 .mu.m deep, with substantially vertical, smooth walls.
After completion of the trenches, a protective conformal layer of PECVD oxide or nitride is applied to cover the silicon beams/structures to a thickness of about 0.3 .mu.m thick. The conformal dielectric layer covers the top surfaces of the surrounding substrate (or mesa), the defined structures, and the sides and the bottom wall of the trench, so it is necessary to remove the dielectric from the trench bottom wall, as by an anisotropic CF.sub.4 /O.sub.2 RIE at 10 mT. This etch does not require a mask, but removes 0.3 .mu.m of dielectric from the beam and mesa top surfaces and from the trench bottom, leaving the side wall coating undisturbed. As a result, the beam is left with a top surface layer and a side wall layer of dielectric, with the bottom of the trench being film-free.
A deep RIE or CAIBE is then used to etch the trench floor down below the lower edge of the sidewall dielectric. This etch preferably exposes 3 to 5 .mu.m of substrate underneath the dielectric on each side of the beams and under the dielectric on the walls of the surrounding mesa, and it is this exposed substrate under the beams and on the mesa walls which is to be removed during the release step. The release is carried out by an isotropic RIE which etches the substrate out from under the beams or other structures, thus releasing them, and etching the substrate on the mesa walls to form cavities. The etch has high selectivity to the dielectric, allowing several microns of substrate to be etched without appreciably affecting the protective dielectric coating. After release, the beams are held cantilevered over the bottom wall of the deep silicon trench by their connections to the surrounding mesa at their ends, for example.
Each released, cantilevered structure has a core of semiconductor material such as single crystal silicon and a conformal coating of dielectric surrounding it on the top surface and side walls. The structural beams may be cantilevered at the ends and free-floating in the center, for example. To activate the structure, either by measuring its motion or by driving it into motion, a metal layer is required. Accordingly, as a final step, an aluminum layer is sputter deposited onto the beam top surface and side walls of the beam, onto the floor of the trenches, and onto the top surface and side walls of the surrounding mesa. The structure is now complete and simply needs to be connected to suitable circuitry to activate it. The circuitry may be on a separate substrate or may be formed in the wafer adjacent the location of the beam prior to fabrication of the beam. It may also be desirable, depending on the application, to add a thin passivation oxide layer 100 to 200 nm thick to prevent shorting between moving structures.
Although the foregoing single mask process has numerous advantages in low temperature applications, and permits fabrication of a wide variety of microelectromechanical structures, there is a need for making single crystal silicon released microstructures which can be electrically isolated from each other while remaining mechanically interconnected. Such structures can be difficult to make using the process described above.